DTXSTS=Val_0x0, CNTCLR=Val_0x0, CNTPRST=Val_0x0
Operation Mode Register
| DTXSTS | Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset, the Tx packet status received from the MAC is forwarded to the application. 0 (Val_0x0): Drop transmit status is disabled 1 (Val_0x1): Drop transmit status is enabled |
| CNTPRST | Counters Preset When this bit is set, The ETH_MTL_TXQ0_UNDERFLOW register is initialized/preset to 0x7F0. The ETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT[MISPKTCNT] and ETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT[OVFPKTCNT] fields are initialized/preset to 0x7F0. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0 (Val_0x0): Counters preset is disabled 1 (Val_0x1): Counters preset is enabled |
| CNTCLR | Counters Reset When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle. If this bit is set along with CNT_PRESET, the CNT_PRESET has precedence. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0 (Val_0x0): Counters are not reset 1 (Val_0x1): All counters are reset |